Researchers Achieve Breakthrough in Laser-Drilling Technology for Next-Generation Semiconductor Chips
A team of researchers, including members from the University of Tokyo, Ajinomoto Fine-Techno Co., Mitsubishi Electric Corp., and Spectronix Corp., has achieved a significant breakthrough in laser-drilling technology. They have successfully created the world's smallest circuit board holes, measuring a mere 3 micrometers in diameter. This advancement is crucial for the development of next-generation semiconductor chips, which require increasingly smaller and more efficient components.
The current standard for micro via holes on circuit boards is 40 micrometers, which is significantly larger than the 5 micrometers or smaller required for high-density semiconductor chips used in generative artificial intelligence and other high-performance technologies. This size discrepancy creates limitations in terms of space and efficiency.
To address this challenge, the research team developed a novel laser-drilling method that involves placing layers of an insulator on a sheet of copper-covered glass. They then utilize a high-powered laser with an extremely short wavelength, guided by a fully-automated AI processing simulation developed by the University of Tokyo researchers. This precise and controlled process allows for the creation of incredibly small and accurate holes.
This breakthrough is expected to significantly improve the speed and design flexibility of the chip-making process. It will also contribute to the introduction of the next-generation semiconductor chip, paving the way for advancements in various fields, including artificial intelligence, high-performance computing, and beyond.
"Our achievement this time marks an important milestone for the subsequent process of finishing semiconductor chips," said Yohei Kobayashi, an applied physics professor at the University of Tokyo's Institute for Solid State Physics. "This method will allow circuit boards to be processed flexibly at low cost to cater to the increasingly dwarfed size of semiconductor chips.