World's Tiniest Circuit Board Holes Drilled, Paving Way for Next-Gen Semiconductor Chips

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World's Tiniest Circuit Board Holes Drilled, Paving Way for Next-Gen Semiconductor Chips

Researchers Achieve Breakthrough in Laser-Drilling Technology for Next-Generation Semiconductor Chips

A team of researchers has achieved a significant breakthrough in laser-drilling technology, successfully creating the world's tiniest circuit board holes measuring a mere 3 micrometers in diameter. This advancement holds immense potential for the development of next-generation semiconductor chips, addressing the growing demand for smaller and more efficient devices.

The research team, comprised of experts from the University of Tokyo, Ajinomoto Fine-Techno Co., Mitsubishi Electric Corp., and Spectronix Corp., recognized the need for micro via holes on circuit boards with diameters of 5 micrometers or smaller. These holes are crucial for high-density semiconductor chips, which are essential for generative artificial intelligence and other high-performance technologies. However, the standard 40-micrometer holes used in current circuit boards occupy too much space, hindering the miniaturization of these chips.

To overcome this challenge, the researchers developed a novel laser-drilling method. This method involves placing layers of an insulator on a sheet of copper-covered glass. A high-powered laser with an extremely short wavelength, guided by a fully-automated AI processing simulation developed by the University of Tokyo researchers, then drills the incredibly small holes with precision.

This breakthrough is expected to significantly enhance the speed and design flexibility of the chip-making process. It is also anticipated to contribute to the introduction of the next-generation semiconductor chip, paving the way for even more powerful and efficient devices in the future.

"Our achievement this time marks an important milestone for the subsequent process of finishing semiconductor chips," said Yohei Kobayashi, an applied physics professor at the University of Tokyo's Institute for Solid State Physics. "This method will allow circuit boards to be processed flexibly at low cost to cater to the increasingly dwarfed size of semiconductor chips.