Intel research shows how to shrink computing chips

Intel research shows how to shrink computing chips

Reuters research teams at Intel Corp on Saturday unveiled work that it believes will help keep speeding up and shrinking computing chips over the next ten years, with several technologies aimed at stacking parts of chips on top of each other.

Intel's Research Components Group presented the work in papers at an international conference in San Francisco. The Silicon Valley company is trying to regain a lead in making the smallest, fastest chips that it has lost to rivals like Taiwan Semiconductor Manufacturing Co and Samsung Electronics Co Ltd in recent years.

The research work unveiled Saturday gave a look into how Intel plans to compete beyond 2025, while Pat Gelsinger laid out commercial plans aimed at regaining that lead by 2025.

One of the ways Intel is packing more computing power into chips is by stacking up tiles or chiplets in three dimensions rather than making chips all as one two-dimensional piece. Intel showed Saturday work that could allow for 10 times as many connections between stacked tiles, so that more complex tiles can be stacked on top of one another.

A research paper showing a way to stack transistors, small switches that form the most basic building bocks of chips by representing the 1 s and 0 s of digital logic on top of one another, was the biggest advance shown on Saturday.

Intel believes that the technology will yield a 30% to 50% increase in the number of transistors it can pack into a given area on a chip. The number of transistors is the main reason chips have gotten faster over the past 50 years.

Paul Fischer, the director and senior principal engineer of Intel's Components Research Group, told Reuters in an interview that "we're clearly saving area by stacking the devices directly on top of each other." We're reducing interconnect lengths and saving energy, so we're making this more cost efficient and better performing.